This invention relates generally to logic latches and multiplexers and, more particularly, to selecting between a number of input signals and to storing the state of the selected signal along a long path in an integrated circuit or cross-chip interconnect.
The operating speed of integrated circuits, such as microprocessors, is continually increasing. Typical high-speed integrated circuits have a clock cycle frequency greater than one gigahertz. In these devices, it is desirable to communicate data signals as quickly as possible. Buffers or repeaters are conventionally used along integrated circuit wire routes or in cross-chip interconnections to regenerate a degrading signal or to maintain fast transition times. Some cross-chip interconnections also need multiplexers to select between a number of input signals. For example, the data bus returning from a large on-chip cache contains multiplexer to implement block redundancy and latches to implement pipeline stages. As clock cycle frequency increases, clock cycle period becomes shorter, which makes it difficult for signals to propagate between circuit elements during one clock cycle period. Pipelining of a long wire or cross-chip interconnect is needed to preserve data integrity and meet timing constraints.
One conventional approach to pipelining or to multiplexing long wire paths is to insert a standard latch or multiplexer in the wire path. This approach suffers, however, from poor performance. Typical latches and multiplexers have insertion delay and poor signal regeneration or signal driving characteristics. Regenerating the driving signal consumes further valuable time.
Another conventional technique is building a latch into an ordinary buffer. An ordinary buffer commonly includes two inverters in series. In a conventional CMOS design, the inverters are each formed from an NFET and a PFET transistor. Clock gating devices are commonly placed in series with the input NFET and input PFET devices. A problem with this technique is that adding clock gating devices along the critical path adds significant delay. Although faster than inserting a standard latch and regenerating the driving signal, this technique is expensive in chip area, clock power, and delay.
A conventional multiplexer can be used to select between a number of input signals. In a conventional multiplexer, the transistors that implement the select function are series-stacked onto the input nodes. Inserting a multiplexer and a latch can cause a significant delay of 3 to 6 data inversions along the critical path.
What is therefore needed is a repeater or buffer multiplexer latch that is efficient as a buffer, a multiplexer, and a data latch, that has low additional insertion delay, and that consumes little clock power.
In an embodiment of the invention, a multiplexer is integrated into a complement reset latch. The complement reset multiplexer latch performs efficiently as a long wire signal repeater, a data latch, and a multiplexer. That is, a complement reset multiplexer latch is used to select between a number of input data signals, to regenerate the selected input data signal, and to hold an output signal at a stored value. Additionally, there is no latch insertion delay because the critical paths of the underlying complement reset buffer are unaffected by the latch transistors. The multiplexer insertion delay is nearly zero as well. The multiplexer functionality adds a single FET side-branch load per critical path, rather than conventionally series-stacking the select transistors. The latch clock FETs are small devices that consume little power. Clock devices in the non-critical multiplexer paths are doubled in number versus the complement reset latch. This results in a clock load that is approximately 5 times smaller than a conventional latch. A complement reset multiplexer latch allows for efficient design of cross-chip paths, such as cache memory interfaces. Because a complement reset multiplexer latch is built into a complement reset buffer, complement reset buffers and complement reset latches can be easily replaced with complement reset multiplexer latches where needed to meet timing or datapath constraints.
In another embodiment of the present invention, a multiplexer is integrated into a complement reset buffer. The complement reset multiplexer does not include the data latch functionality of the complement reset multiplexer latch. The complement reset multiplexer is a buffer or repeater with an integrated low insertion delay multiplexer for applications that do not require the output signal to be held at a store value.